The demand for high performance computers requires that state-of-the-art microprocessors execute instructions in the minimum amount of time. A number of different approaches have been taken to decrease instruction execution time, thereby increasing processor throughput. One way to increase processor throughput is to use a pipeline architecture in which the processor is divided into separate processing stages that form the pipeline. Instructions are broken down into elemental steps that are executed in different stages in an assembly line fashion.
A pipelined processor is capable of executing several different machine instructions concurrently. This is accomplished by breaking down the processing steps for each instruction into several discrete processing phases, each of which is executed by a separate pipeline stage. Hence, each instruction must pass sequentially through each pipeline stage in order to complete its execution. In general, a given instruction is processed by only one pipeline stage at a time, with one clock cycle being required for each stage. Since instructions use the pipeline stages in the same order and typically only stay in each stage for a single clock cycle, an N stage pipeline is capable of simultaneously processing N instructions. When filled with instructions, a processor with N pipeline stages completes one instruction each clock cycle.
The execution rate of an N-stage pipeline processor is theoretically N times faster than an equivalent non-pipelined processor. A non-pipelined processor is a processor that completes execution of one instruction before proceeding to the next instruction. Typically, pipeline overheads and other factors decrease somewhat the execution rate advantage that a pipelined processor has over a non-pipelined processor.
An exemplary seven stage processor pipeline may consist of an address generation stage, an instruction fetch stage, a decode stage, a read stage, a pair of execution (E1 and E2) stages, and a write (or write-back) stage. In addition, the processor may have an instruction cache that stores program instructions for execution, a data cache that temporarily stores data operands that otherwise are stored in processor memory, and a register file that also temporarily stores data operands.
The address generation stage generates the address of the next instruction to be fetched from the instruction cache. The instruction fetch stage fetches an instruction for execution from the instruction cache and stores the fetched instruction in an instruction buffer. The decode stage takes the instruction from the instruction buffer and decodes the instruction into a set of signals that can be directly used for executing subsequent pipeline stages. The read stage fetches required operands from the data cache or registers in the register file. The E1 and E2 stages perform the actual program operation (e.g., add, multiply, divide, and the like) on the operands fetched by the read stage and generates the result. The write stage then writes the result generated by the E1 and E2 stages back into the data cache or the register file.
Assuming that each pipeline stage completes its operation in one clock cycle, the exemplary seven stage processor pipeline takes seven clock cycles to process one instruction. As previously described, once the pipeline is full, an instruction can theoretically be completed every clock cycle.
The throughput of a processor also is affected by the size of the instruction set executed by the processor and the resulting complexity of the instruction decoder. Large instruction sets require large, complex decoders in order to maintain a high processor throughput. However, large complex decoders tend to increase power dissipation, die size and the cost of the processor. The throughput of a processor also may be affected by other factors, such as exception handling, data and instruction cache sizes, multiple parallel instruction pipelines, and the like. All of these factors increase or at least maintain processor throughput by means of complex and/or redundant circuitry that simultaneously increases power dissipation, die size and cost.
In many processor applications, the increased cost, increased power dissipation, and increased die size are tolerable, such as in personal computers and network servers that use x86-based processors. These types of processors include, for example, Intel Pentium™ processors and AMD Athlon™ processors.
However, in many applications it is essential to minimize the size, cost, and power requirements of a data processor. This has led to the development of processors that are optimized to meet particular size, cost and/or power limits. For example, the recently developed Transmeta Crusoe™ processor greatly reduces the amount of power consumed by the processor when executing most x86 based programs. This is particularly useful in laptop computer applications. Other types of data processors may be optimized for use in consumer appliances (e.g., televisions, video players, radios, digital music players, and the like) and office equipment (e.g., printers, copiers, fax machines, telephone systems, and other peripheral devices). The general design objectives for data processors used in consumer appliances and office equipment are the minimization of cost and complexity of the data processor.
Another way to increase processor throughput is to use bypass circuitry in a pipeline architectures to transfer the result of a calculation or other operation from one pipeline stage to another pipeline stage before the result is finalized by writing it to a register file. For example, a first instruction may add the contents of Register A to Register B and store the resulting sum in Register C. A second and subsequent instruction may multiply the sum in Register C by 5 and store the resulting product in Register D. Without bypass circuitry, the second instruction must wait until after the sum from the first instruction is written to Register D before the second instruction can proceed. This stalls the instruction pipeline. Bypass circuitry allows the sum from the first instruction to be transferred directly from the adder that produced the sum (i.e., while the result is still in the execution stage) to one of the inputs of the multiplier addressed by the second instruction. Thus, the multiplication may occur while (or before) the sum is being written to Register C.
Unfortunately, bypassing circuitry complicates the operation of a microprocessor when a cache miss occurs. When a target address is applied to a data cache, the target address is decoded and applied to a data array and a tag array. Data from the selected entry in the data array is output from the data cache. At the same time, address bits (i.e., tags) from the selected entry in the tag array are output from the tag array and compared to the target address to determine if a cache miss or cache hit has occurred. However, due to the delay associated with the address comparison circuitry that determines if a cache miss or cache hit occurred, the data fetched from the target address in the data array may be transferred to, and stored in, other pipeline stages by the bypass circuitry before it is determined that a cache miss has occurred. The common solution to this problem is to flush the entire pipeline whenever a cache miss occurs. Unfortunately, this also results in additional delays as the pipeline stages are flushed and reloaded.
Therefore, there is a need in the art for improved pipeline architectures for use in data processors. In particular, there is a need for processor pipeline architectures that minimize delays associated with data cache misses. More particularly, there is a need for processor pipeline architectures that implement bypass circuitry that sustains a minimum performance degradation when a data cache miss occurs.